1. Field of the Invention
The present invention relates to an address generation apparatus for generating an address, and in particular, to an address generation apparatus for generating an address which indicates a position of data in a memory, the position being used for accessing the data stored in the memory.
2. Description of the Related Art
Recently, DSPs (digital signal processors) have been widely used as the field of digital signal processing has expanded. A DSP reads a plurality of pieces of data (typically, two systems of data) stored in a memory and executes various operations (e.g., multiplication and addition) on the plurality of pieces of data. In order to access the data stored in the memory, an address indicating the position of the data in the memory is used. For accessing the plurality of pieces of data stored in the memory, the DSP usually has a plurality of special registers storing a plurality of addresses, respectively. For example, two addresses are output to the memory from two special registers. As a result, two pieces of data corresponding to the two addresses are output from the memory. A prescribed operation is performed on the two pieces of data.
FIG. 4 shows a structure of a conventional address generation apparatus 900. The address generation apparatus 900 includes an address register file 910 and a modifying register file 940.
The address register file 910 includes a plurality of registers, for example, four 16-bit registers (hereinafter, referred to as xe2x80x9cregisters R0, R1, R2 and R3xe2x80x9d).
The modifying register file 940 includes a plurality of registers, for example, four 16-bit registers (hereinafter, referred to as xe2x80x9cregister MR0, MR1, MR2 and MR3xe2x80x9d).
FIG. 5 shows an exemplary arrangement of data groups stored in a data memory 950 (FIG. 4). In the example shown in FIG. 5, six data groups, i.e., data groups A through data groups F are stored in the data memory 950.
With reference to FIGS. 4 and 5, an operation of the address generation apparatus 900 will be described.
A leading address of the data group A is stored in advance in the register R0 in the address register file 910. A leading address of the data group B is stored in advance in the register R1 in the address register file 910. The address generation apparatus 900 outputs the contents of the registers R0 and R1 to the data memory 950 as addresses 920 and 922. The data memory 950 outputs data stored at a position designated by the address 920 to a data bus 960, and outputs data stored at a position designated by the address 922 to a data bus 962. A data processing unit 970 performs a prescribed operation on the two pieces of data output to the data buses 960 and 962.
An adder 930 adds the contents in the address 920 and the register MR0 and writes the addition result into the register R0. Thus, the content of the register R0 is updated.
An adder 932 adds the contents in the address 922 and the register MR1 and writes the addition result into the register R1. Thus, the content of the register R1 is updated.
For example, when the content of each of the registers MR0 and MR1 is xe2x80x9c1xe2x80x9d, the content of each of the registers R0 and R1 is incremented by 1. In accordance with the output from the register R0 (i.e., address 920), the data is sequentially read from the leading address of the data group A stored in the data memory 950. In accordance with the output from the register R1 (i.e., address 922), the data is sequentially read from the leading address of the data group B stored in the data memory 950. Thus, a prescribed operation is performed on the data in the data group A and the data in the data group B.
For performing a prescribed operation on data in data group C and data in data group D stored in the data memory 950, a leading address of the data group C is stored in advance in the register R2 and a leading address of the data group D is stored in advance in the register R3. In a similar manner to that described above, data in the data group C and data in the data group D are read from the data memory 950 and a prescribed operation is performed on the two pieces of data read from data memory 950.
For performing a prescribed operation on data in data group E and data in data group F stored in the data memory 950, contents of registers R0 and R1 need to be newly set in the following manner.
In the case where the content of the register R0 is necessary, the content is pushed onto the data memory 950 through the data bus 960. In the case where the content of the register R1 is necessary, the content is pushed onto the data memory 950 through the data bus 960. Then, a leading address of the data group E is stored in the register R0, and a leading address of the data group F is stored in the register R1. Next, in a similar manner to that described above, data in the data group E and data in the data group F are read from the data memory 950, and a prescribed operation is performed on the two pieces of data read from the data memory 950. (See, for example, xe2x80x9cDSP 56116 User""s Manualxe2x80x9d, Motorola Japan, Ltd. (1992), page 26.)
In the above-described conventional technology, the contents of the registers R0 and R1 need to be pushed before the leading addresses of the data groups E and F are stored in the registers R0 and R1. This involves a problem in that additional steps are required to set a leading address of a data group in a register included in the address register file 910.
FIG. 6 shows an exemplary program for generating an address using the conventional address generation apparatus 900, in which the above-described problem is conspicuous. In FIG. 6, xe2x80x9cLOOPxe2x80x9d is an instruction to execute an instruction subsequent to xe2x80x9cLOOPxe2x80x9d repeatedly, and xe2x80x9cENDLOOPxe2x80x9d is an instruction to terminate the repeated execution. xe2x80x9cLOOP Xxe2x80x9d represents that an instruction between LOOP X and ENDLOOP is executed X times. As shown in FIG. 6, when the leading addresses of the data groups are set in the registers R0 and R1 using a double loop, at least 6xc3x97Xxc3x97N steps are required to set the leading addresses. This significantly lowers the operating efficiency of the DSP.
The number of steps required to set the leading addresses of the data groups can be reduced by increasing the number of registers included in the address register file 910. However, when the number of registers included in the address register file 910 is increased, the circuit delay by a selection circuit (included in the address register file 910) for outputting the addresses 920 and 922 is extended. Accordingly, such a solution is not suitable for a high speed operation. Furthermore, such an increase in the number of registers increases the number of signals written in the register, resulting in an increase in power consumption.
An address generation apparatus for generating a first address and a second address according to the present invention includes a first register for storing a first reference address; a second register for storing a second reference address; a third register for storing a first offset value with respect to the first reference address, the first offset value being designated by an instruction; a fourth register for storing a second offset value with respect to the second reference address, the second offset value being designated by the instruction; a first adder for adding the first reference address stored in the first register and the first offset value stored in the third register; a second adder for adding the second reference address stored in the second register and the second offset value stored in the fourth register; a fifth register for storing an output from the first adder as the first address; and a sixth register for storing an output from the second adder as the second address.
In one embodiment of the invention, the first reference address is a leading address of one of a plurality of data groups stored in a data memory, and the second reference address is a leading address of another one of the plurality of data groups stored in the data memory.
In one embodiment of the invention, the instruction includes a first immediate value section and a second immediate value section, and the first offset value is designated by the first immediate value section and the second offset value is designated by the second immediate value section.
In one embodiment of the invention, the addition performed by the first adder and the storage of the output from the first adder to the fifth register, and the addition performed by the second adder and the storage of the output from the second adder to the sixth register are achieved by executing the instruction.
Thus, the invention described herein makes possible the advantage of providing an address generation apparatus for efficiently generating an address of data in a memory.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.